Lustre V6 to verilog

This tutorial illustrates

• the use of the -verilog option of the lv6 compiler that generates Verilog programs.
• how to simulate such programs using Verilator
• how to use the Lustre toolset to perform interactive simulations of Verilog programs.

In order to ease the installation process of the various necessary tools, we suppose that you have working Guix installation

Guix based environment

We first clone the lv6 git repo in order to get Lustre program examples and the necessary guix files.

git clone https://gricad-gitlab.univ-grenoble-alpes.fr/verimag/synchrone/lustre-v6.git

then, in order to get a working environment with all the necessary tools installed, you just need to:

cd lustre-v6
guix time-machine -C channels.scm -- shell -CP -m guixVerilo/manifest.scm

or even better, on linux, the following ougth to work and should allow you to use graphical (X11-based) tools:

guix time-machine -C channels.scm -- shell -CP -m guixVerilo/manifest.scm --preserve='^DISPLAY$' --share=/tmp/.X11-unix

Warning: it can be quite long the first time you run this command!

Your first lustre-v6-based verilog simulation

Once guix has finished to download and compile everything, you should be able to generate a Verilog program from a Lustre one:

mkdir TestVerilog
cd TestVerilog
cp ../test/should_work/watchdog.lus .
lv6 -verilog watchdog.lus -n watchdog

In order to simulate the generated Verilog program (watchdog.v), you need to generate a Verilog Test Bench:

generate_tb watchdog.v watchdogV watchdog-tb.cpp

compile it with verilator:

verilator --cc watchdog.v --exe watchdog-tb.cpp --build > /dev/null

and you can simulate it:

./obj_dir/Vwatchdog

or better, if the $DISPLAY has been set correctly, you can provide inputs with luciole:

luciole-rif ./obj_dir/Vwatchdog